Designing and fabricating electronic systems typically involves many steps, known as a “design flow.” The design flow typically starts with transforming a specification for a new electronic system into a logical design. The logical design can describe the electronic system in terms of both the exchange of signals, for example, between hardware registers, and the logical operations that can be performed on those signals. In some examples, the logical design can model the electronic system at a register transfer level (RTL) level of design abstraction using a Hardware Description Language (HDL), such as SystemVerilog, Very high speed integrated circuit Hardware Description Language (VHDL), or the like.
The design flow can include “functional verification” of the logical design, for example, determining whether the logical design accurately performs intended functions of the electronic system. Typically, software and hardware “tools” can perform functional verification operations, such as simulating, emulating, prototyping, and/or formally verifying the logical design. For example, a computing system implementing a design verification tool can simulate functionality described in the logical design and provide transactions or sets of test vectors to the simulated logical design. The computing system implementing the design verification tool can determine whether the logical design describes circuitry configured to accurately perform the intended functions of the electronic system based on how the simulated logical design responded to the transactions or test vectors.
Emulation and prototyping systems can include programmable logic devices, such as field-programmable gate arrays (FPGAs), which include integrated circuitry capable of being configured to implement the electronic system described in the logical design. The logical design can be synthesized from the register transfer level into a gate-level representation, such as a netlist, and then compiled into a format capable of configuring the programmable logic devices in the emulation and prototyping systems to implement the electronic system described in the logical design. In some examples, the synthesis operations can include RTL synthesis, which can generate generic gates corresponding to the functionality described in the logical design, and include physical synthesis or compilation, which can map the generic gates to one or more target programmable logic devices, for example, generating a target device-specific netlist. The emulation and prototyping systems can be configured with the target device-specific netlist to implement the electronic system associated with the logical design.
The emulation and prototyping systems may include hardware-based features that, when utilized to implement the logic design, would introduce delay between registers or other clock-driven circuitry. Some of these hardware-based features can introduce signal propagation delays, for example, due to transitions between different programmable logic devices, between different printed circuit boards, between different chassis, between different sub-sections of logic on a programmable logic device, or the like. The hardware-based features also can introduce signal translation delays, such as through power domain crossings, time-domain multiplexing delay, Serializer/Deserializer (SERDES) delay, or the like. The addition of the delay introduced by these hardware-based features can increase a worst case delay between registers or other clock-driven circuitry implemented in the emulation and prototyping systems, which can result in the emulation and prototyping systems reducing the frequency of a system clock to accommodate the worst case delay and thus slowing operation of the emulation and prototyping systems.
Some emulation and prototyping systems attempt to offset a portion of this system speed reduction by altering the synthesis of the logical design, for example, by selecting which portions of the logical design should include the delays due to the signal transitions and signal translations. While a thoughtful configuration of the emulation and prototyping systems with the logical design may reduce an impact the additional delay has on overall system speed, it typically comes at a cost of increased compilation time or synthesis time due to the added complexity in design constraints.